library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

library lib_expoRNS;

entity exponentiation_bench is
  --port(
  --   a_reel : out std_logic_vector(8-1 downto 0);
  --   S_reel : out std_logic_vector(8-1 downto 0)
  --  );
end exponentiation_bench;


architecture expo_bench1 of exponentiation_bench is



  component exponentiation_unit
    generic (
      Z          : positive range 1 to 256 := 8;
      N : positive := 255 ;
      R : positive := 256;
      k : positive := 1;
      montgomery : boolean := true);
    port (
      reset : in std_logic;
      clk : in std_logic;
      bit_utile : in std_logic_vector(8-1 downto 0);
      a     : in std_logic_vector(8-1 downto 0);
      p : in std_logic_vector(8-1 downto 0);
      start : in std_logic;
      fin : out std_logic;
      S : out std_logic_vector(8-1 downto 0)
      );
  end component;
  signal clk,start,reset,fin : std_logic := '0';
  signal bit_utile,a,S,p : std_logic_vector(8-1 downto 0) := (others => '0');
begin  -- expo_bench1

  expo : exponentiation_unit port map ( reset, clk, bit_utile, a,p, start, fin, S );
  clk <= not clk after 10 ns;
--  a_reel <= resize(unsigned(a)*256 mod 255,8);
--  s_reel <= resize(unsigned(S)*256 mod 255,8);
  process
    constant delay_exp : time := 1000 ns;
    constant delay_reset : time := 10 ns;
  begin
    reset <= '1';
    a      <= "00010001";
    bit_utile <= "00000011";
    p <="00000101";

    wait for delay_reset ;
    reset <= '0';
    start <= '1';

    wait for delay_exp;
  end process;
end expo_bench1;
